Information Center for ARM

Example description

  
ADC_ADC3_DMA ADC3 conversion using DMA for Data transfer


Example Description 

This example describes how to use the ADC3 and DMA to transfer continuously 
converted data from ADC3 to memory.
The ADC3 is configured to convert continuously channel7.
Each time an end of conversion occurs the DMA transfers, in circular mode, the
converted data from ADC3 DR register to the ADC3ConvertedValue variable.

In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2. 
Since ADC3 clock is 30 MHz and sampling time is set to 3 cycles, the total 
conversion time is 0.5 us (2Msps).

User can vary the ADC3 channel7 voltage using the Eval Board potentiometer
The converted voltage is displayed on the Eval Board LCD (when the define PRINT_ON_LCD
is enabled in main.c)


Directory contents 

  - ADC/ADC3_DMA/system_stm32f2xx.c   STM32F2xx system clock configuration file
  - ADC/ADC3_DMA/stm32f2xx_conf.h     Library Configuration file
  - ADC/ADC3_DMA/stm32f2xx_it.c       Interrupt handlers
  - ADC/ADC3_DMA/stm32f2xx_it.h       Interrupt handlers header file
  - ADC/ADC3_DMA/main.c               Main program

	  The "system_stm32f2xx.c" is generated by an automatic clock configuration 
      tool and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. 


Hardware and Software environment 

  - This example runs on STM32F2xx Devices.
  
  - This example has been tested with STM322xG-EVAL RevB and can be easily tailored
    to any other development board.

  - STM322xG-EVAL Set-up
    - Use the Potentiometer (RV1) of the Eval board (connected to PF.09). 

===============================================================================

DualADC_Interleaved_DMAmode3  Use ADC1 and ADC2 in Dual interleaved mode and DMA mode3

Example Description 

This example provides a short description of how to use the ADC peripheral to
convert a regular channel in Dual interleaved mode using DMA in mode 3 with 5Msps.

DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.

The Dual interleaved delay is configured 6 ADC clk cycles.

On each DMA request (two data items are available) two bytes representing two 
ADC-converted data items are transferred as a half word.
The data transfer order is similar to that of the DMA mode 2.

A DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0] 
2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]

The ADC1 and ADC2 are configured to convert ADC Channel 12, with conversion 
triggered by software.
By this way, ADC channel 12 is converted each 6 cycles.

In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2.
Since ADCCLK= 30MHz and Conversion rate = 6 cycle
==> Conversion Time = 30M/6cyc = 5Msps.

Refer to "simulation.xls" file to have the diagram simulation of the example.

Directory contents 

  - ADC/DualADC_Interleaved_DMAmode3/system_stm32f2xx.c   STM32F2xx system clock configuration file
  - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_conf.h     Library Configuration file
  - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.h       Interrupt handlers header file
  - ADC/DualADC_Interleaved_DMAmode3/stm32f2xx_it.c       Interrupt handlers
  - ADC/DualADC_Interleaved_DMAmode3/main.c               Main program

The "system_stm32f2xx.c" is generated by an automatic clock configuration 
      tool and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. 

Hardware and Software environment 

  - This example runs on STM32F2xx Devices.

  - This example has been tested with STM322xG-EVAL RevB and can be easily tailored
    to any other development board

  - STM322xG-EVAL Set-up 
    - Connect PC.2 to a power supply (do not forget to connect the power supply 
      GND to the EVAL board GND)

===============================================================================

DualADC_RegulSimu_DMAmode1  Use ADC1 and ADC2 in Dual regular simultaneous mode and DMA mode1

Example Description 

This example provides a short description of how to use the ADC peripheral to
convert regular channels simultaneously in dual mode using DMA in mode 1.

Regular simultaneous mode is performed on a regular group of channels. 
In Dual ADC mode, ADC1 data are transferred on the first request, ADC2 data are
transferred on the second request and so on.
On each DMA request (one data item is available), a half-word representing an
ADC-converted data item is transferred.
The conversion is triggered by software.

The ADC1 is configured to convert ADC Channel 10 and 11.
The ADC2 is configured to convert ADC Channel 11 and 12.

Note: the sequence length must be the same for both ADCs

In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2.
So ADCCLK= 30MHz 

Conversion rate of channel 10 and 12 = 30 cycles => Conversion Time = 30M/30cyc = 1Msps.
Conversion rate of channel 11 = 15 cycles => Conversion Time = 30M/15cyc = 2Msps.

Refer to "simulation.xls" file to have the diagram simulation of the example.


Directory contents 

  - ADC/DualADC_RegulSimu_DMAmode1/system_stm32f2xx.c   STM32F2xx system clock configuration file
  - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_conf.h     Library Configuration file
  - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.h       Interrupt handlers header file
  - ADC/DualADC_RegulSimu_DMAmode1/stm32f2xx_it.c       Interrupt handlers
  - ADC/DualADC_RegulSimu_DMAmode1/main.c               Main program


The "system_stm32f2xx.c" is generated by an automatic clock configuration 
      tool and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. 


Hardware and Software environment 

  - This example runs on STM32F2xx Devices.

  - This example has been tested with STM322xG-EVAL RevB and can be easily tailored
    to any other development board.

  - STM322xG-EVAL Set-up 
    - Connect PC.0, PC.1 and PC.2 to a power supply (do not forget to connect the
      power supply GND to the EVAL board GND)

===============================================================================

TripleADC_Interleaved_DMAmode2  Use ADC1, ADC2 and ADC3 in Triple interleaved mode and DMA mode2 with 6Msps 

Example Description 

This example provides a short description of how to use the ADC peripheral to 
convert a regular channel in Triple interleaved mode using DMA in mode 2 with 
6Msps .

The Triple interleaved delay is configured 5 ADC clk cycles.

In Triple ADC mode, three DMA requests are generated: 
- On the first request, both ADC2 and ADC1 data are transferred (ADC2 data take 
  the upper half-word and ADC1 data take the lower half-word). 
- On the second request, both ADC1 and ADC3 data are transferred (ADC1 data take
  the upper half-word and ADC3 data take the lower half-word).
- On the third request, both ADC3 and ADC2 data are transferred (ADC3 data take 
  the upper half-word and ADC2 data take the lower half-word) and so on.

On each DMA request (two data items are available) two half-words representing 
two ADC-converted data items are transferred as a word.

A DMA request is generated each time 2 data items are available :
1st request: ADC_CDR[31:0] = (ADC2_DR[15:0] << 16) | ADC1_DR[15:0] (step1)
2nd request: ADC_CDR[31:0] = (ADC1_DR[15:0] << 16) | ADC3_DR[15:0] (step2)
3rd request: ADC_CDR[31:0] = (ADC3_DR[15:0] << 16) | ADC2_DR[15:0] (step3)
4th request: ADC_CDR[31:0] = (ADC2_DR[15:0] << 16) | ADC1_DR[15:0] (step1) and so on.

The conversion is triggered by software.

The ADC1, ADC2 and ADC3 are configured to convert ADC Channel 12.
By this way, the ADC can reach 6Msps, in fact the same channel is converted
each 5 cycles

In this example, the system clock is 120MHz, APB2 = 60MHz and ADC clock = APB2 /2. 
Since ADCCLK= 30MHz and Conversion rate = 5 cycles 
==> Conversion Time = 30M/5cyc = 6Msps

Refer to "simulation.xls" file to have the diagram simulation of the example.

Directory contents 

  - ADC/TripleADC_Interleaved_DMAmode2/system_stm32f2xx.c   STM32F2xx system clock configuration file
  - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_conf.h     Library Configuration file
  - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.h       Interrupt handlers header file
  - ADC/TripleADC_Interleaved_DMAmode2/stm32f2xx_it.c       Interrupt handlers
  - ADC/TripleADC_Interleaved_DMAmode2/main.c               Main program


	  The "system_stm32f2xx.c" is generated by an automatic clock configuration 
      tool and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool. 

      
Hardware and Software environment 

  - This example runs on STM32F2xx Devices.
  
  - This example has been tested with STM322xG-EVAL RevB and can be easily tailored
    to any other development board.

  - STM322xG-EVAL Set-up 
    - Connect PC.2 to a power supply (do not forget to connect the power supply GND
      to the EVAL board GND)

===============================================================================
	  
ADC_VBAT_Measurement ADC_VBAT_Measurement

Example Description 

This example describes how to measure VBAT voltage using ADC1 regular channel 18.
In fact, the measured value correspond to VBAT/2; as the VBAT voltage could be higher
than VDDA, to ensure the correct operation of the ADC, the VBAT pin is internally
connected to a bridge divider by 2.

In this example the VBAT/2 voltage is continuously converted, each time an end
of conversion occurs the DMA transfers, in circular mode, the converted data from 
ADC1 DR register to the ADCConvertedValue variable.  
However, in real application to prevent any unwanted consumption on the battery,
it is recommended to enable the bridge divider only when needed for ADC
conversion then disable it.

User can display the VBAT voltage on the Eval Board LCD (when the define PRINT_ON_LCD
is enabled in main.c)

In this example, the system clock is 120MHz, APB2 =60MHz and ADC clock = APB2 /2.
So ADCCLK= 30MHz 

Conversion rate of Vbat channel  = Sampling Time + Conversion Time = 15 + 12 cycles
                                 = 27 cycles ==> Conversion Time = 30MHz/27cyc = 1.11Msps.


Directory contents 

  - ADC/VBAT_Measurement/system_stm32f2xx.c   STM32F2xx system clock configuration file 
  - ADC/VBAT_Measurement/stm32f2xx_conf.h     Library Configuration file
  - ADC/VBAT_Measurement/stm32f2xx_it.c       Interrupt handlers
  - ADC/VBAT_Measurement/stm32f2xx_it.h       Interrupt handlers header file
  - ADC/VBAT_Measurement/main.c               Main program

	  The "system_stm32f2xx.c" is generated by an automatic clock configuration
      tool and can be easily customized to your own configuration. 
      To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.


Hardware and Software environment 

  - This example runs on STM32F2xx Devices.

  - This example has been tested with STM322xG-EVAL RevB and can be easily tailored
    to any other development board