Example description
TIM_6Steps TIM 6 Steps example
Example Description
This example shows how to configure the TIM1 peripheral to generate 6 Steps.
The STM32F2xx TIM1 peripheral offers the possibility to program in advance the
configuration for the next TIM1 outputs behaviour (step) and change the configuration
of all the channels at the same time. This operation is possible when the COM
(commutation) event is used.
The COM event can be generated by software by setting the COM bit in the TIM1_EGR
register or by hardware (on TRC rising edge).
In this example, a software COM event is generated each 100 ms: using the SysTick
interrupt.
The TIM1 is configured in Timing Mode, each time a COM event occurs, a new TIM1
configuration will be set in advance.
The break Polarity is used at High level.
The following Table describes the TIM1 Channels states:
-----------------------------------------------
| Step1 | Step2 | Step3 | Step4 | Step5 | Step6 |
----------------------------------------------------------
|Channel1 | 1 | 0 | 0 | 0 | 0 | 1 |
----------------------------------------------------------
|Channel1N | 0 | 0 | 1 | 1 | 0 | 0 |
----------------------------------------------------------
|Channel2 | 0 | 0 | 0 | 1 | 1 | 0 |
----------------------------------------------------------
|Channel2N | 1 | 1 | 0 | 0 | 0 | 0 |
----------------------------------------------------------
|Channel3 | 0 | 1 | 1 | 0 | 0 | 0 |
----------------------------------------------------------
|Channel3N | 0 | 0 | 0 | 0 | 1 | 1 |
----------------------------------------------------------
Directory contents
- TIM/6Steps/stm32f2xx_conf.h Library Configuration file
- TIM/6Steps/stm32f2xx_it.c Interrupt handlers
- TIM/6Steps/stm32f2xx_it.h Interrupt handlers header file
- TIM/6Steps/main.c Main program
- TIM/6Steps/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG Set-up
- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
- TIM1_CH3 pin (PA.10)
- TIM1_CH1N pin (PB.13)
- TIM1_CH2 pin (PE.11)
- TIM1_CH3N pin (PB.15)
- TIM1_CH1 pin (PA.08)
- TIM1_CH2N pin (PB.14)
- Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a
break event, switch this pin level from 0V to 3.3V.
===============================================================================
TIM_7PWM_Output TIM_7PWM_Output
Example Description
This example shows how to configure the TIM1 peripheral to generate 7 PWM signals
with 4 different duty cycles (50%, 37.5%, 25% and 12.5%).
TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
SystemCoreClock is set to 120 MHz for STM32F2xx devices.
The objective is to generate 7 PWM signal at 17.57 KHz:
- TIM1_Period = (SystemCoreClock / 17570) - 1
The channel 1 and channel 1N duty cycle is set to 50%
The channel 2 and channel 2N duty cycle is set to 37.5%
The channel 3 and channel 3N duty cycle is set to 25%
The channel 4 duty cycle is set to 12.5%
The Timer pulse is calculated as follows:
- ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
The TIM1 waveform can be displayed using an oscilloscope.
Directory contents
- TIM/7PWM_Output/stm32f2xx_conf.h Library Configuration file
- TIM/7PWM_Output/stm32f2xx_it.c Interrupt handlers
- TIM/7PWM_Output/stm32f2xx_it.h Interrupt handlers header file
- TIM/7PWM_Output/main.c Main program
- TIM/7PWM_Output/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
- TIM1_CH1 pin (PA.08)
- TIM1_CH1N pin (PB.13)
- TIM1_CH2 pin (PE.11)
- TIM1_CH2N pin (PB.14)
- TIM1_CH3 pin (PA.10)
- TIM1_CH3N pin (PB.15)
- TIM1_CH4 pin (PA.11)
===============================================================================
TIM_Cascade_Synchro TIM Cascade Synchro example
Example Description
This example shows how to synchronize TIM peripherals in cascade mode.
In this example three timers are used:
Timers synchronisation in cascade mode:
1/TIM2 is configured as Master Timer:
- PWM Mode is used
- The TIM2 Update event is used as Trigger Output
2/TIM3 is slave for TIM2 and Master for TIM4,
- PWM Mode is used
- The ITR1(TIM2) is used as input trigger
- Gated mode is used, so start and stop of slave counter
are controlled by the Master trigger output signal(TIM2 update event).
- The TIM3 Update event is used as Trigger Output.
3/TIM4 is slave for TIM3,
- PWM Mode is used
- The ITR2(TIM3) is used as input trigger
- Gated mode is used, so start and stop of slave counter are controlled by the
Master trigger output signal(TIM3 update event).
The TIM2 counter clock is 60 MHz.
The Master Timer TIM2 is running at TIM2 frequency :
TIM2 frequency = (TIM2 counter clock)/ (TIM2 period + 1) = 234.375 KHz
and the duty cycle = TIM2_CCR1/(TIM2_ARR + 1) = 25%.
The TIM3 is running at:
(TIM2 frequency)/ (TIM3 period + 1) = 58.593 KHz and a duty cycle equal
to TIM3_CCR1/(TIM3_ARR + 1) = 25%
The TIM4 is running at:
(TIM3 frequency)/ (TIM4 period + 1) = 14.648 Hz and a duty cycle equal
to TIM4_CCR1/(TIM4_ARR + 1) = 25%
Directory contents
- TIM/Cascade_Synchro/stm32f2xx_conf.h Library Configuration file
- TIM/Cascade_Synchro/stm32f2xx_it.c Interrupt handlers
- TIM/Cascade_Synchro/stm32f2xx_it.h Interrupt handlers header file
- TIM/Cascade_Synchro/main.c Main program
- TIM/Cascade_Synchro/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG Set-up
- Connect the following pins to an oscilloscope to monitor the different
waveforms:
- TIM2 CH1 (PA.00)
- TIM3 CH1 (PB.04)
- TIM4 CH1 (PB.06)
===============================================================================
TIM_ComplementarySignals TIM Complementary Signals example
Example Description
This example shows how to configure the TIM1 peripheral to generate three
complementary TIM1 signals, to insert a defined dead time value, to use the break
feature and to lock the desired parameters.
TIM1CLK is fixed to SystemCoreClock, the TIM1 Prescaler is equal to 0 so the
TIM1 counter clock used is SystemCoreClock (120MHz).
The objective is to generate PWM signal at 17.57 KHz:
- TIM1_Period = (SystemCoreClock / 17570) - 1
The Three Duty cycles are computed as the following description:
The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
The Timer pulse is calculated as follows:
- ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
A dead time equal to 11/SystemCoreClock is inserted between the different
complementary signals, and the Lock level 1 is selected.
The break Polarity is used at High level.
The TIM1 waveform can be displayed using an oscilloscope.
Directory contents
- TIM/ComplementarySignals/stm32f2xx_conf.h Library Configuration file
- TIM/ComplementarySignals/stm32f2xx_it.c Interrupt handlers
- TIM/ComplementarySignals/stm32f2xx_it.h Interrupt handlers header file
- TIM/ComplementarySignals/main.c Main program
- TIM/ComplementarySignals/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG Set-up
- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
- TIM1_CH1 pin (PA.08)
- TIM1_CH1N pin (PB.13)
- TIM1_CH2 pin (PE.11)
- TIM1_CH2N pin (PB.14)
- TIM1_CH3 pin (PA.10)
- TIM1_CH3N pin (PB.15)
- Connect the TIM1 break pin TIM1_BKIN pin (PB.12) to the GND. To generate a
break event, switch this pin level from 0V to 3.3V.
===============================================================================
TIM_DMA TIM DMA example
Example Description
This example provides a description of how to use DMA with TIM1 Update request
to transfer Data from memory to TIM1 Capture Compare Register3.
TIM1CLK = SystemCoreClock, Prescaler = 0, TIM1 counter clock = SystemCoreClock
SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB.
The objective is to configure TIM1 channel 3 to generate complementary PWM
signal with a frequency equal to 17.57 KHz:
- TIM1_Period = (SystemCoreClock / 17570) - 1
and a variable duty cycle that is changed by the DMA after a specific number of
Update DMA request.
The number of this repetitive requests is defined by the TIM1 Repetion counter,
each 3 Update Requests, the TIM1 Channel 3 Duty Cycle changes to the next new
value defined by the SRC_Buffer.
Directory contents
- TIM/DMA/stm32f2xx_conf.h Library Configuration file
- TIM/DMA/stm32f2xx_it.c Interrupt handlers
- TIM/DMA/stm32f2xx_it.h Interrupt handlers header file
- TIM/DMA/main.c Main program
- TIM/DMA/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the TIM1 pins to an oscilloscope to monitor the different waveforms:
- TIM1 CH3 (PA.10)
- TIM1 CH3N (PB.15)
===============================================================================
TIM1_DMABURST TIM1 DMA Burst transfer example
Example Description
This example shows how to update the TIM1 channel1 period and the duty cycle
using the TIM1 DMA burst feature.
Every update DMA request, the DMA will do 3 transfers of half words into Timer
registers beginning from ARR register.
On the DMA update request, 0x0FFF will be transferred into ARR, 0x0000
will be transferred into RCR, 0x0555 will be transferred into CCR1.
The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
clock at 24 MHz the Prescaler is computed as following:
- Prescaler = (TIM1CLK / TIM1 counter clock) - 1
SystemCoreClock is set to 120 MHz.
The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
= 24 MHz / 4096 = 5.8 KHz
The TIM1 CCR1 register value is equal to 0x555, so the TIM1 Channel 1 generates a
PWM signal with a frequency equal to 5.8 KHz and a duty cycle equal to 33.33%:
TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR + 1)* 100 = 33.33%
The PWM waveform can be displayed using an oscilloscope.
No need of RCR update, but we should do it because of the ARR and CCR1
mapping.
Directory contents
- TIM/DMABurst/stm32f2xx_conf.h Library Configuration file
- TIM/DMABurst/stm32f2xx_it.c Interrupt handlers
- TIM/DMABurst/stm32f2xx_it.h Interrupt handlers header file
- TIM/DMABurst/main.c Main program
- TIM/DMABurst/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the following pins to an oscilloscope to monitor the different
waveforms:
- TIM1 CH1 (PA.08)
===============================================================================
TIM_ExtTrigger_Synchro TIM External Trigger Synchro example
Example Description
This example shows how to synchronize TIM peripherals in cascade mode with an
external trigger.
In this example three timers are used:
1/TIM1 is configured as Master Timer:
- Toggle Mode is used
- The TIM1 Enable event is used as Trigger Output
2/TIM1 is configured as Slave Timer for an external Trigger connected to TIM1
TI2 pin (TIM1 CH2 configured as input pin):
- The TIM1 TI2FP2 is used as Trigger Input
- Rising edge is used to start and stop the TIM1: Gated Mode.
3/TIM3 is slave for TIM1 and Master for TIM4,
- Toggle Mode is used
- The ITR1(TIM1) is used as input trigger
- Gated mode is used, so start and stop of slave counter
are controlled by the Master trigger output signal(TIM1 enable event).
- The TIM3 enable event is used as Trigger Output.
4/TIM4 is slave for TIM3,
- Toggle Mode is used
- The ITR2(TIM3) is used as input trigger
- Gated mode is used, so start and stop of slave counter
are controlled by the Master trigger output signal(TIM3 enable event).
The TIM1CLK is fixed to 120 MHZ, the Prescaler is equal to 4 so the TIMx clock
counter is equal to 24 MHz.
The TIM3CLK and TIM4CLK are fixed to 60 MHZ, the Prescaler is equal to 4
so the TIMx clock counter is equal to 12 MHz.
The Three Timers are running at:
TIMx frequency = TIMx clock counter/ 2*(TIMx_Period + 1) = 162.1 KHz.
The starts and stops of the TIM1 counters are controlled by the external trigger.
The TIM3 starts and stops are controlled by the TIM1, and the TIM4 starts and
stops are controlled by the TIM3.
Directory contents
- TIM/ExtTrigger_Synchro/stm32f2xx_conf.h Library Configuration file
- TIM/ExtTrigger_Synchro/stm32f2xx_it.c Interrupt handlers
- TIM/ExtTrigger_Synchro/stm32f2xx_it.h Interrupt handlers header file
- TIM/ExtTrigger_Synchro/main.c Main program
- TIM/ExtTrigger_Synchro/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect an external trigger, with a frequency <= 40KHz, to the TIM1 CH2
pin (PE.11). In this example the frequency is equal to 5 KHz.
- Connect the following pins to an oscilloscope to monitor the different waveforms:
- TIM1 CH1 (PA.08)
- TIM3 CH1 (PB.04)
- TIM4 CH1 (PB.06)
===============================================================================
TIM_Input_Capture TIM Input Capture example
Example Description
This example shows how to use the TIM peripheral to measure the frequency of an
external signal.
The TIMxCLK frequency is set to SystemCoreClock /2 (Hz), the Prescaler is 0 so the
TIM1 counter clock is SystemCoreClock (Hz)/2.
SystemCoreClock is set to 120 MHz.
TIM1 is configured in Input Capture Mode: the external signal is connected to
TIM1 Channel2 used as input pin.
To measure the frequency we use the TIM1 CC2 interrupt request,
so In the TIM1_CC_IRQHandler routine, the frequency of the external signal is computed.
The "TIM1Freq" variable contains the external signal frequency:
TIM1Freq = TIM1 counter clock / Capture in Hz,
where the Capture is the difference between two consecutive TIM1 captures.
The minimum frequency value to measure is 1100 Hz.
Directory contents
- TIM/InputCapture/stm32f2xx_conf.h Library Configuration file
- TIM/InputCapture/stm32f2xx_it.c Interrupt handlers
- TIM/InputCapture/stm32f2xx_it.h Interrupt handlers header file
- TIM/InputCapture/main.c Main program
- TIM/InputCapture/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the external signal to measure to the TIM1 CH2 pin (PE.11).
===============================================================================
TIM_OCActive TIM_OCActive
Example Description
This example shows how to configure the TIM peripheral to generate four different
signals with four different delays.
The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
to get TIM3 counter clock at 1 KHz so the Prescaler is computed as following:
- Prescaler = (TIM3CLK / TIM3 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB.
The TIM3 CCR1 register value is equal to 1000:
TIM3_CH1 delay = CCR1_Val/TIM3 counter clock = 1000 ms
so the TIM3 Channel 1 generates a signal with a delay equal to 1000 ms.
The TIM3 CCR2 register value is equal to 500:
TIM3_CH2 delay = CCR2_Val/TIM3 counter clock = 500 ms
so the TIM3 Channel 2 generates a signal with a delay equal to 500 ms.
The TIM3 CCR3 register value is equal to 250:
TIM3_CH3 delay = CCR3_Val/TIM3 counter clock = 250 ms
so the TIM3 Channel 3 generates a signal with a delay equal to 250 ms.
The TIM3 CCR4 register value is equal to 125:
TIM3_CH4 delay = CCR4_Val/TIM3 counter clock = 125 ms
so the TIM3 Channel 4 generates a signal with a delay equal to 125 ms.
The delay correspond to the time difference between PG.06 and TIM3_CHx signal
rising edges.
Directory contents
- TIM/OCActive/stm32f2xx_conf.h Library Configuration file
- TIM/OCActive/stm32f2xx_it.c Interrupt handlers
- TIM/OCActive/stm32f2xx_it.h Interrupt handlers header file
- TIM/OCActive/main.c Main program
- TIM/OCActive/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the following pins to an oscilloscope to monitor the different
waveforms:
- Use LED1 connected to PG.06
- PC.06 (TIM3_CH1)
- PC.07 (TIM3_CH2)
- PC.08 (TIM3_CH3)
- PC.09 (TIM3_CH4)
===============================================================================
TIM_OCInactive TIM_OCInactive
Example Description
This example shows how to configure the TIM peripheral in Output Compare Inactive
mode with the corresponding Interrupt requests for each channel.
The TIM2CLK frequency is set to SystemCoreClock / 2 (Hz), and the objective is
to get TIM2 counter clock at 1 KHz so the Prescaler is computed as following:
- Prescaler = (TIM2CLK / TIM2 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx devices
The TIM2 CCR1 register value is equal to 1000:
TIM2_CC1 delay = CCR1_Val/TIM2 counter clock = 1000 ms
so the PC.06 is reset after a delay equal to 1000 ms.
The TIM2 CCR2 register value is equal to 500:
TIM2_CC2 delay = CCR2_Val/TIM2 counter clock = 500 ms
so the PC.07 is reset after a delay equal to 500 ms.
The TIM2 CCR3 register value is equal to 250:
TIM2_CC3 delay = CCR3_Val/TIM2 counter clock = 250 ms
so the PC.08 is reset after a delay equal to 250 ms.
The TIM2 CCR4 register value is equal to 125:
TIM2_CC4 delay = CCR4_Val/TIM2 counter clock = 125 ms
so the PC.09 is reset after a delay equal to 125 ms.
While the counter is lower than the Output compare registers values, which
determines the Output delay, the PG.06, PG.08, PI.09 and PC.07 pin are turned on.
When the counter value reaches the Output compare registers values, the Output
Compare interrupts are generated and, in the handler routine, these pins are turned off.
Directory contents
- TIM/OCInactive/stm32f2xx_conf.h Library Configuration file
- TIM/OCInactive/stm32f2xx_it.c Interrupt handlers
- TIM/OCInactive/stm32f2xx_it.h Interrupt handlers header file
- TIM/OCInactive/main.c Main program
- TIM/OCInactive/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09
and PC.07 pins and connect them an oscilloscope to monitor the different
waveforms.
===============================================================================
TIM_OCToggle TIM_OCToggle
Example Description
This example shows how to configure the TIM3 peripheral to generate four different
signals with four different frequencies.
The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), and we want to get TIM3
counter clock at 15 MHz so the Prescaler is computed as following:
- Prescaler = (TIM3CLK / TIM3 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx devices
The TIM3 CCR1 register value is equal to 40961:
CC1 update rate = TIM3 counter clock / CCR1_Val = 366.2 Hz,
so the TIM3 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz.
The TIM3 CCR2 register is equal to 20480:
CC2 update rate = TIM3 counter clock / CCR2_Val = 732.4 Hz
so the TIM3 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz.
The TIM3 CCR3 register is equal to 10240:
CC3 update rate = TIM3 counter clock / CCR3_Val = 1464.8 Hz
so the TIM3 channel 3 generates a periodic signal with a frequency equal to 732.4 Hz.
The TIM3 CCR4 register is equal to 5120:
CC4 update rate = TIM3 counter clock / CCR4_Val = 2929.6 Hz
so the TIM3 channel 4 generates a periodic signal with a frequency equal to 1464.8 Hz.
Directory contents
- TIM/OCToggle/stm32f2xx_conf.h Library Configuration file
- TIM/OCToggle/stm32f2xx_it.c Interrupt handlers
- TIM/OCToggle/stm32f2xx_it.h Interrupt handlers header file
- TIM/OCToggle/main.c Main program
- TIM/OCToggle/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the TIM3 pins to an oscilloscope to monitor the different waveforms:
- PC.06 (TIM3_CH1)
- PC.07 (TIM3_CH2)
- PC.08 (TIM3_CH3)
- PC.09 (TIM3_CH4)
===============================================================================
TIM_OnePulse TIM One Pulse example
Example Description
This example shows how to use the TIM peripheral to generate a One pulse Mode
after a Rising edge of an external signal is received in Timer Input pin.
TIM2CLK = SystemCoreClock/2, we want to get TIM2 counter clock at 30 MHz:
- Prescaler = (TIM2CLK / TIM2 counter clock) - 1
SystemCoreClock is set to 120 MHz.
The Autoreload value is 65535 (TIM4->ARR), so the maximum frequency value to
trigger the TIM4 input is 30000000/65535 = 458 Hz.
The TIM4 is configured as follows:
The One Pulse mode is used, the external signal is connected to TIM4 CH2 pin (PB.07),
the rising edge is used as active edge, the One Pulse signal is output
on TIM4_CH1 (PB.06).
The TIM_Pulse defines the delay value, the delay value is fixed to:
delay = CCR1/TIM4 counter clock = 16383 / 30000000 = 546.1 us.
The (TIM_Period - TIM_Pulse) defines the One Pulse value, the pulse value is fixed to:
One Pulse value = (TIM_Period - TIM_Pulse)/TIM4 counter clock
= (65535 - 16383) / 30000000 = 1.638 ms.
Directory contents
- TIM/OnePulse/stm32f2xx_conf.h Library Configuration file
- TIM/OnePulse/stm32f2xx_it.c Interrupt handlers
- TIM/OnePulse/stm32f2xx_it.h Interrupt handlers header file
- TIM/OnePulse/main.c Main program
- TIM/OnePulse/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the external signal to the TIM4_CH2 pin (PB.07)
- Connect the TIM4_CH1 (PB.06) pin to an oscilloscope to monitor the waveform.
===============================================================================
TIM_Parallel_Synchro TIM Parallel Synchro example
Example Description
This example shows how to synchronize TIM peripherals in parallel mode.
In this example three timers are used:
Timers synchronisation in parallel mode:
1/TIM2 is configured as Master Timer:
- PWM Mode is used
- The TIM2 Update event is used as Trigger Output
2/TIM3 and TIM4 are slaves for TIM2,
- PWM Mode is used
- The ITR1(TIM2) is used as input trigger for both slaves
- Gated mode is used, so starts and stops of slaves counters are controlled
by the Master trigger output signal(update event).
The TIM2 counter clock is 60 MHz.
The Master Timer TIM2 is running at TIM2 frequency:
TIM2 frequency = TIM2 counter clock/ (TIM2 period + 1) = 234.375 KHz
and the duty cycle is equal to TIM2_CCR1/(TIM2_ARR + 1) = 25%.
The TIM3 is running at:
(TIM2 frequency)/ (TIM3 period + 1) = 23.437 KHz and a duty cycle equal to
TIM3_CCR1/(TIM3_ARR + 1) = 30%
The TIM4 is running at:
(TIM2 frequency)/ (TIM4 period + 1) = 46.875 KHz and a duty cycle equal to
TIM4_CCR1/(TIM4_ARR + 1) = 60%
Directory contents
- TIM/Parallel_Synchro/stm32f2xx_conf.h Library Configuration file
- TIM/Parallel_Synchro/stm32f2xx_it.c Interrupt handlers
- TIM/Parallel_Synchro/stm32f2xx_it.h Interrupt handlers header file
- TIM/Parallel_Synchro/main.c Main program
- TIM/Parallel_Synchro/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the pins to an oscilloscope to monitor the different waveforms:
- TIM2 CH1 (PA.00)
- TIM3 CH1 (PC.06)
- TIM4 CH1 (PB.06)
===============================================================================
TIM_PWM_Input TIM_PWM_Input
Example Description
This example shows how to use the TIM peripheral to measure the frequency and
duty cycle of an external signal.
The TIMxCLK frequency is set to SystemCoreClock/4 (Hz), the Prescaler is 0 so the
counter clock is SystemCoreClock/2 (Hz).
SystemCoreClock is set to 120 MHz fro STM32F2xx Devices RevA, RevZ and RevB.
TIM4 is configured in PWM Input Mode: the external signal is connected to
TIM4 Channel2 used as input pin.
To measure the frequency and the duty cycle we use the TIM4 CC2 interrupt request,
so In the TIM4_IRQHandler routine, the frequency and the duty cycle of the external
signal are computed.
The "Frequency" variable contains the external signal frequency:
TIM4 counter clock = SystemCoreClock / 2,
Frequency = TIM4 counter clock / TIM4_CCR2 in Hz,
The "DutyCycle" variable contains the external signal duty cycle:
DutyCycle = (TIM4_CCR1*100)/(TIM4_CCR2) in %.
The minimum frequency value to measure is 915 Hz (TIM4 counter clock / CCR MAX).
Directory contents
- TIM/PWM_Input/stm32f2xx_conf.h Library Configuration file
- TIM/PWM_Input/stm32f2xx_it.c Interrupt handlers
- TIM/PWM_Input/stm32f2xx_it.h Interrupt handlers header file
- TIM/PWM_Input/main.c Main program
- TIM/PWM_Input/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the external signal to measure to the TIM4 CH2 pin (PB.07).
===============================================================================
TIM_PWM_Output TIM_PWM_Output
Example Description
This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation)
mode.
The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter
clock at 20 MHz the Prescaler is computed as following:
- Prescaler = (TIM3CLK / TIM3 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB.
The TIM3 is running at 30 KHz: TIM3 Frequency = TIM3 counter clock/(ARR + 1)
= 20 MHz / 666 = 30 KHz
The TIM3 CCR1 register value is equal to 500, so the TIM3 Channel 1 generates a
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 50%:
TIM3 Channel1 duty cycle = (TIM3_CCR1/ TIM3_ARR + 1)* 100 = 50%
The TIM3 CCR2 register value is equal to 375, so the TIM3 Channel 2 generates a
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 37.5%:
TIM3 Channel2 duty cycle = (TIM3_CCR2/ TIM3_ARR + 1)* 100 = 37.5%
The TIM3 CCR3 register value is equal to 250, so the TIM3 Channel 3 generates a
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 25%:
TIM3 Channel3 duty cycle = (TIM3_CCR3/ TIM3_ARR + 1)* 100 = 25%
The TIM3 CCR4 register value is equal to 125, so the TIM3 Channel 4 generates a
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 12.5%:
TIM3 Channel4 duty cycle = (TIM3_CCR4/ TIM3_ARR + 1)* 100 = 12.5%
The PWM waveform can be displayed using an oscilloscope.
Directory contents
- TIM/PWM_Output/stm32f2xx_conf.h Library Configuration file
- TIM/PWM_Output/stm32f2xx_it.c Interrupt handlers
- TIM/PWM_Output/stm32f2xx_it.h Interrupt handlers header file
- TIM/PWM_Output/main.c Main program
- TIM/PWM_Output/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the following pins to an oscilloscope to monitor the different
waveforms:
- PC.06: (TIM3_CH1)
- PC.07: (TIM3_CH2)
- PC.08: (TIM3_CH3)
- PC.09: (TIM3_CH4)
===============================================================================
TIM_TIM1_Synchro TIM1 Synchro example
Example Description
This example shows how to synchronize TIM1 and Timers (TIM3 and TIM4) in parallel mode.
Timers synchronisation in parallel mode:
1/ TIM1 is configured as Master Timer:
- PWM Mode is used
- The TIM1 Update event is used as Trigger Output
2/ TIM3 and TIM4 are slaves for TIM1,
- PWM Mode is used
- The ITR0(TIM1) is used as input trigger for both slaves
- Gated mode is used, so starts and stops of slaves counters
are controlled by the Master trigger output signal(update event).
The TIM1 counter clock is 120 MHz.
The Master Timer TIM1 is running at:
TIM1 frequency = TIM1 counter clock / (TIM1_Period + 1) = 468.750 KHz
and the duty cycle is equal to: TIM1_CCR1/(TIM1_ARR + 1) = 50%
The TIM3 is running at:
(TIM1 frequency)/ ((TIM3 period +1)* (Repetition_Counter+1)) = 31.250 KHz and
a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 33.3%
The TIM4 is running at:
(TIM1 frequency)/ ((TIM4 period +1)* (Repetition_Counter+1)) = 46.875 KHz and
a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 50%
Directory contents
- TIM/TIM1_Synchro/stm32f2xx_conf.h Library Configuration file
- TIM/TIM1_Synchro/stm32f2xx_it.c Interrupt handlers
- TIM/TIM1_Synchro/stm32f2xx_it.h Interrupt handlers header file
- TIM/TIM1_Synchro/main.c Main program
- TIM/TIM1_Synchro/system_stm32f2xx.c STM32F2xx system source file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the following pins to an oscilloscope to monitor the different waveforms:
- TIM1 CH1 (PA.08)
- TIM3 CH1 (PC.06)
- TIM4 CH1 (PB.06)
===============================================================================
TIM10_PWMOutput TIM10_PWMOutput
Example Description
This example shows how to configure the TIM peripheral in PWM (Pulse Width Modulation)
mode.
The TIM10CLK frequency is set to SystemCoreClock(Hz), to get TIM10 counter
clock at 20 MHz the Prescaler is computed as following:
- Prescaler = (TIM10CLK / TIM10 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx Devices RevA, RevZ and RevB.
The TIM10 is running at 30 KHz: TIM10 Frequency = TIM10 counter clock/(ARR + 1)
= 20 MHz / 666 = 30 KHz
The TIM10 CCR1 register value is equal to 500, so the TIM10 Channel 1 generates a
PWM signal with a frequency equal to 30 KHz and a duty cycle equal to 50%:
TIM10 Channel1 duty cycle = (TIM10_CCR1/ TIM10_ARR + 1)* 100 = 50%
The PWM waveform can be displayed using an oscilloscope.
Directory contents
- TIM/TIM10_PWMOutput/stm32f2xx_conf.h Library Configuration file
- TIM/TIM10_PWMOutput/stm32f2xx_it.c Interrupt handlers
- TIM/TIM10_PWMOutput/stm32f2xx_it.h Interrupt handlers header file
- TIM/TIM10_PWMOutput/main.c Main program
- TIM/TIM10_PWMOutput/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the following pin to an oscilloscope PF.06: (TIM10_CH1)
===============================================================================
TIM_TIM9_OCToggle TIM_TIM9_OCToggle
Example Description
This example shows how to configure the TIM9 peripheral to generate four different
signals with four different frequencies.
The TIM9CLK frequency is set to SystemCoreClock (Hz), and we want to get TIM9
counter clock at 15 MHz so the Prescaler is computed as following:
- Prescaler = (TIM9CLK / TIM9 counter clock) - 1
SystemCoreClock is set to 120 MHz for STM32F2xx devices
The TIM9 CCR1 register value is equal to 40961:
CC1 update rate = TIM9 counter clock / CCR1_Val = 366.2 Hz,
so the TIM9 Channel 1 generates a periodic signal with a frequency equal to 183.1 Hz.
The TIM9 CCR2 register is equal to 20480:
CC2 update rate = TIM9 counter clock / CCR2_Val = 732.4 Hz
so the TIM9 channel 2 generates a periodic signal with a frequency equal to 366.3 Hz.
Directory contents
- TIM/TIM9_OCToggle/stm32f2xx_conf.h Library Configuration file
- TIM/TIM9_OCToggle/stm32f2xx_it.c Interrupt handlers
- TIM/TIM9_OCToggle/stm32f2xx_it.h Interrupt handlers header file
- TIM/TIM9_OCToggle/main.c Main program
- TIM/TIM9_OCToggle/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Connect the TIM9 pins to an oscilloscope to monitor the different waveforms:
- PA.02 (TIM9_CH1)
- PA.03 (TIM9_CH2)
===============================================================================
TIM_TimeBase TIM_TimeBase
Example Description
This example shows how to configure the TIM peripheral in Output Compare Timing
mode with the corresponding Interrupt requests for each channel in order to generate
4 different time bases.
The TIM3CLK frequency is set to SystemCoreClock / 2 (Hz), to get TIM3 counter
clock at 6 MHz so the Prescaler is computed as following:
- Prescaler = (TIM3CLK / TIM3 counter clock) - 1
SystemCoreClock is set to 120MHz for STM32F2xx Devices RevA, RevZ and RevB.
The TIM3 CC1 register value is equal to 40961,
CC1 update rate = TIM3 counter clock / CCR1_Val = 146.48 Hz,
so the TIM3 Channel 1 generates an interrupt each 6.8ms
The TIM3 CC2 register is equal to 27309,
CC2 update rate = TIM3 counter clock / CCR2_Val = 219.7 Hz
so the TIM3 Channel 2 generates an interrupt each 4.55ms
The TIM3 CC3 register is equal to 13654,
CC3 update rate = TIM3 counter clock / CCR3_Val = 439.4Hz
so the TIM3 Channel 3 generates an interrupt each 2.27ms
The TIM3 CC4 register is equal to 6826,
CC4 update rate = TIM3 counter clock / CCR4_Val = 878.9 Hz
so the TIM3 Channel 4 generates an interrupt each 1.13ms.
When the counter value reaches the Output compare registers values, the Output
Compare interrupts are generated and, in the handler routine, 4 pins(PG.06, PG.08,
PI.09 and PC.07) are toggled with the following frequencies:
- PG.06: 73.24Hz (CC1)
- PG.08: 109.8Hz (CC2)
- PI.09: 219.7Hz (CC3)
- PC.07: 439.4Hz (CC4)
Directory contents
- TIM/TimeBase/stm32f2xx_conf.h Library Configuration file
- TIM/TimeBase/stm32f2xx_it.c Interrupt handlers
- TIM/TimeBase/stm32f2xx_it.h Interrupt handlers header file
- TIM/TimeBase/main.c Main program
- TIM/TimeBase/system_stm32f2xx.c STM32F2xx system clock configuration file
The "system_stm32f2xx.c" is generated by an automatic clock configuration
tool and can be easily customized to your own configuration.
To select different clock setup, use the "STM32F2xx_Clock_Configuration_V1.0.0.xls" tool.
Hardware and Software environment
- This example runs on STM32F2xx Devices.
- This example has been tested with STM322xG-EVAL RevB and can be easily tailored
to any other development board.
- STM322xG-EVAL Set-up
- Use LED1, LED2, LED3 and LED4 connected respectively to PG.06, PG.08, PI.09
and PC.07 pins and connect them on an oscilloscope to show the different
Time Base signals.